1. Field of the Invention
This invention relates generally to an apparatus for testing a redundant memory. More particularly, the present invention relates to an apparatus for testing a redundant memory which is equipped with a failure data memory device which is suitable for the analysis of failure data needed for determining a remedy line, during a test on a memory incorporating therein redundant word lines or bit lines for remedying defective bits.
2. Description of the Prior Art
Heretofore known memory-testing apparatuses (hereinafter referred to as "memory testers") usually comprise a pattern generator 1 which is controlled by a timing signal output 6 from a timing generator 2, a comparator 4 which compares data output 11 from a memory 3 under test with expected-value data 10 and outputs a judgement result 12 on the memory 3 under test, and a failure memory 5 constructed so that fail data is written into the address thereof which is the same as an address 8 given to the memory 3 under test, or corresponds thereto, when the comparison result from the comparator 12 is "failure," as illustrated in FIG. 1.
The pattern generator 1 provides the address 8 and a test pattern 9 as write data for the memory 3 under test and, at the same time, provides the expectedvalue data 10 for the comparator 4 and outputs a control signal 7 to the timing generator 2.
The failure memory 5 is generally constructed of a memory which has a capacity which is the same as, or greater than, the capacity of the memory 3 under test, and which can be read from and written to. The same addresses 8 as those given to the memory 3 under test are also given to the failure memory 5 by the pattern generator 1.
However, as memory capacities have become larger, a recent technical trend has been directed to improving the production process in order to improve the production yield, which has dropped with the increase in memory capacity. An attempt has also been made to improve the yield by improving the memory device itself. In other words, a method is now employed in which any defective bits in the memory are remedied by replacing them in line units by redundant bit lines or word lines incorporated in the memory.
FIG. 3 illustrates an example of remedying a memory in which failures 1 through 13, represented by Xs as test results (where numerals within circles represent the sequence in which the failures have occurred), are remedied by two lines on the column side (x) and two lines on the row side (y) that have been prepared as redundant remedy lines.
The example shown in FIG. 3 makes it possible to remedy the failed cells 1 through 13 of the tested memory cell array 16 by two redundant lines on each of the column and row sides, but this remedy can sometimes not be used, depending on the distribution of failure occurrences and the number of failed cells. The line numbers of the redundant remedy lines along the column and row sides will be hereinafter called N.sub.x and N.sub.y, respectively.
Data analysis for judging whether or not a remedy is possible from the distribution and number of failure data, and for determining the remedy lines, is conventionally carried out using the data within the failure memory 5 of FIG. 1, after the test is completed. However, this remedy processing should not be considered simply as the collection of data on test results, but should rather be regarded as a part of the production process for completing the memory. Accordingly, processing on an on-line, real-time basis within a short period of time is required.
This means that the conventional method described above, merely using a failure memory whose capacity is the same as, or greater than, that of the memory under test which is prepared for the data analysis, is not sufficient because a considerable length of time is needed just for searching the content of the memory to determine the failure addresses. Thus the method can not easily satisfy the requirements for memories with a large capacity.
Moreover, the ratio of the test cost to the memory cost is high, as is well known in the art. To reduce the test cost, therefore, attempts have been made to simultaneously test a large number of memories using a single tester. In such a case, as seen in FIG. 2, it is possible to provide failure memories 5.sub.1 through 5.sub.n which store test results on memories 3.sub.1 through 3.sub.n under test, respectively, as the structure of the tester shown in FIG. 2. Accordingly, the analysis processing for determining remedies for the data in the failure memories 5.sub.1 through 5.sub.n is sequentially carried out by a CPU 13 starting from the failure memory 5.sub.1 and ending at the failure memory 5.sub.n. For this reason, the above problem of processing time becomes even more critical.
From the point of view of hardware size and construction, the memory used as the failure memory 5 must have a faster access time than that of the memory 3 under test. However, a failure memory 5 is usually composed of a combination of a large number of memories of a smaller capacity than that of the memory 3 under test, so that the failure memory data can be easily read out using a CPU 13 or the like. When the construction of peripheral circuits required for controlling the read and write operations for one failure memory 5 is taken into consideration, therefore, the size of the hardware required for one failure memory 5 can not be reduced very easily. Thus, the size and cost of the hardware for the failure memories raises a critical problem for a system in which a large number of memories are simultaneously tested.